Samsung Electronics and SK Hynix are competing in the next generation HBM (High Bandwidth Memory) technology in the United States. Both companies will launch their respective core HBM technologies at the "Hot Chips 2026" global semiconductor design conference in 2026.
Samsung Electronics will focus on showcasing basic chips as data transmission channels, while SK Hynix will showcase advanced packaging technology for stable stacking of DRAM chips and effective heat dissipation. With the continuous advancement of HBM technology, the importance of chip design and stacking methods (such as heat dissipation) seems to be increasing day by day, rather than just speed and capacity.

Samsung Electronics and SK Hynix will jointly debut at the "Hot Chips 2026" conference held at Stanford University in the United States from February 23 to 25, 2026. On the first day of the conference (23rd), Samsung Electronics PL Han Sang wook will give a speech on basic chip technology, while SK Hynix Vice President Lee Jae sik will give a speech on advanced packaging technology.

Hot Chips is the top event in the field of high-performance semiconductors, which began in 1989. This year, many globally renowned companies including NVIDIA, AMD, Intel, and Micron will participate extensively. Due to the conference's main focus on next-generation technologies that can be applied to practical products, it has attracted much attention from the industry.
This year, memory technology is particularly prominent, and the theme of the first special lecture is "Memory Technology". During the conference, a special lecture on memory technology was also arranged. This is because, with the explosive growth of data processed by artificial intelligence (AI), the ability to provide timely memory for this data has become a key factor determining performance. Samsung Electronics will launch a basic chip located at the bottom layer of HBM. This chip connects multiple DRAM chips and GPU computing devices, acting as a gateway to send stored data to the GPU and retrieve and transmit necessary information.
Samsung Electronics' advantage lies in its ability to manufacture this chip using its own manufacturing process. Samsung Electronics operates both memory and semiconductor foundry businesses. The HBM4, which began mass production in February last year, uses Samsung's 4nm process to manufacture the basic chip. This is a strategy to improve performance by combining proprietary DRAM technology with supporting chips. SK Hynix focuses on DRAM packaging that balances both stacking and heat dissipation.
On the same day, SK Hynix will release a solution to reduce heat generation and bending under the theme of "HBM Advanced Packaging". Due to the use of DRAM layer stacking structure in HBM, the higher the stacking height, the greater the heat generation, and the easier it is for the chip to bend. The stability of this structure determines its performance and yield. The representative technology is "Advanced MR-MUF". This method involves filling the gaps between stacked DRAM with liquid protective material and curing it. This can firmly fix the chip and effectively dissipate heat. This technology is also applied to the 12 layer HBM4E delivered to major customers in June last year. Compared with HBM4, HBM4E has reduced thermal resistance by 17% and increased maximum operating speed to 16Gbps per pin.
The presentation themes proposed by the two companies indicate that the competitive landscape has significantly become more complex since the introduction of HBM4. As the data path widens and the number of DRAM stack layers increases, the number of technologies that need to be addressed also increases.
Firstly, the data length has doubled. The number of I/O ports for HBM4 has increased from 1024 for HBM3E to 2048. As the amount of information exchanged simultaneously increases, the burden on the basic chips responsible for organizing this data also increases. Due to the varying demands of each customer for HBM, logical design and manufacturing processes must also be managed accordingly. During the stacking process, heat dissipation becomes a major bottleneck. As the number of layers increases, the heat generation also increases, and the chip must become thinner. If the flexibility and yield issues cannot be solved, it will be difficult to achieve the full performance of DRAM no matter how fast it is.
As a result, the competitive landscape of HBM is evolving from a "speed" competition to a "design and stacking process" competition. An industry insider said, "In the era of artificial intelligence, memory is no longer seen as a simple component. Domestic companies are also expanding their roles, no longer just chip suppliers, but becoming partners in designing artificial intelligence systems with customers